1. Field of the Invention
The present invention generally relates to systems and methods for measuring stress in a specimen. Certain embodiments relate to methods that include determining stress in patterned structures on a specimen using stress-induced birefringence measurements of the patterned structures.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polish, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Semiconductor manufacturing involves fabricating semiconductor devices with many different materials. When dissimilar materials are formed in contact with one another, the materials may exhibit increased stress. For example, when a dielectric thin film is formed on a monocrystalline silicon substrate, stress may be produced in both the dielectric thin film and the monocrystalline silicon substrate. If the stress in either the thin film or the substrate becomes too high, then the thin film and/or the substrate may be damaged. For instance, the thin film may crack and pull away from the wafer thereby necessitating removal and re-formation of the thin film on the substrate. In another example, the substrate may become so warped that it is no longer viable for use in manufacturing semiconductor devices. For example, wafers that are warped may be unsuitable for lithography processes since the focus of the exposure tool will vary across the wafer due to the differences in the position of the uppermost surface of the wafer caused by the warping.
One example of a measurement device that can be used to measure stress in thin films is illustrated in U.S. Pat. No. 6,608,689 to Wei et al., which is incorporated by reference as if fully set forth herein. The systems described in this patent use a bow and warp measurement module to determine the level of stress in a thin film. The bow and warp measurement module measures stress using probe beam displacement information. For example, the amount and direction of the displacement of the probe beam on the detector provides a measure of the wafer local slope. The results of this measurement can be supplied as a known parameter (i.e., level of birefringence) to subsequent determination of the characteristics of the thin film. Therefore, by utilizing a determination of stress (from a measurement of angular displacement of the wafer), the calculations for thin film parameters (e.g., index of refraction n, extinction coefficient k, and thickness t) can be optimized using these measurements. In a similar manner, the system described in this patent can be used to correct stress measurements that are performed as described above using optical measurements of the thin film characteristics. For instance, the bow and warp stress measurements may be corrected for the actual thickness of the thin film formed on the substrate instead of using an assumed thickness value.
Although the systems described by Wei et al. may be useful for measuring stress and other parameters of thin films, these systems do have some limitations. For instance, these systems are not suitable for measuring stress in patterned structures formed on a wafer. In particular, the bow and warp measurements may not represent the stress on patterned structures since the bow and warp measurements are performed across a relatively large area of the wafer and therefore may not accurately reflect the stress proximate the patterned structures. In addition, the patterned structures may not cause a measurable change in the wafer local slope that is measured by the systems described by Wei et al. Therefore, the wafer local slope measurements are not accurate measurements of the stress in the patterned structures. Furthermore, the patterned structures may be formed on or within a material formed on the wafer. As such, a material may be interposed between the patterned structures and the wafer. As a result, any bow and warp measurements would produce measurements of stress caused by the combination of the patterned structures and any other materials present on the wafer. Consequently, these measurements will not accurately reflect the stress that is present in the patterned structures.
Measurement of stress in patterned structures on a wafer, however, is becoming increasingly important. For example, semiconductor patterned areas made of dissimilar materials can develop high levels of stress. These stress levels can degrade both performance and reliability. Two areas where stress is of particular importance are shallow trench isolation (STI) and copper interconnect. In STI, the silicon has submicron wide trenches etched within it, which are filled with silicon dioxide and/or silicon nitride. High levels of stress caused by the dissimilar materials can affect the electrical performance of the transistor and can even lead to cracking in the corners of the trenches. Copper interconnect structures include submicron trenches and round holes etched in dielectric materials such as silicon dioxides and low-k dielectrics. These trenches and holes are filled with copper for connecting transistors to each other to form a circuit. Again, stress can build up and cause problems such as void formation in the copper, even leading to complete breaks in the copper lines thereby forming opening circuits.
Some methods are available for measuring stress in patterned structures. One example of a method for measuring stress in a material is to perform x-ray diffraction (XRD) on a crystalline material in an array of structures on a wafer. Stress will change the spacing between atoms in the crystal, and this change in spacing can be measured with XRD. Another method is to perform Raman spectroscopy on silicon in the array of structures. The phonon spectrum of silicon is changed by stress, and this change in the phonon spectrum can be measured by Raman spectroscopy.
There are, however, several disadvantages to the above-described methods. For example, x-ray diffraction can only be performed on crystalline and polycrystalline materials. This excludes amorphous materials like silicon dioxide and low-k dielectric materials used in semiconductor interconnect structures, which is one area where stress measurement is of particular interest. Crystalline silicon is the only material used in conventional semiconductors where Raman spectroscopy can measure the phonon spectrum. Therefore, XRD and Raman spectroscopy are limited in the types of materials that they can measure. In addition, both XRD and Raman spectroscopy suffer from poor signal-to-noise ratios, and extended integration times are necessary to collect adequate signal levels. These long integration times force the throughput of the measurement systems to be relatively low.
Accordingly, it may be advantageous to develop systems and methods for measuring stress in patterned structures on a specimen that are flexible in the types of materials that can be measured and have sufficient signal-to-noise ratios, throughput, and accuracy.